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PRELIMINARY
CY14B256K
256-Kbit (32K x 8) nvSRAM with Real-Time-Clock
Features
* Data integrity of Cypress nvSRAM combined with full featured real time clock -- Low power, 300 nA Max, RTC current -- Capacitor or battery backup for RTC * Watchdog timer * Clock alarm with programmable interrupts * 25 ns, 35 ns, and 45 ns access times * "Hands-off" automatic STORE on power down with only a small capacitor * STORE to QuantumTrapTM initiated by software, device pin, or on power down * RECALL to SRAM initiated by software or on power up * Infinite READ, WRITE, and RECALL cycles * High reliability -- Endurance to 200K cycles -- Data retention: 20 years @ 55C * 10 mA typical ICC at 200 ns cycle time * Single 3V operation with tolerance of +15%, -10% * Commercial and industrial temperature * SSOP Package (ROHS compliant)
Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile static RAM with a full featured real-time-clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM can be read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. The real-time-clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for one time alarms or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control.
Logic Block Diagram
QuantumTrap 512 X 512
A5 A6 A7 A8 A9 A 11 A 12 A 13 A 14
V CC
V CAP V RTCbat V RTCcap
HSB
STORE
POWER CONTROL STORE/ RECALL CONTROL
ROW DECODER
STATIC RAM ARRAY 512 X 512
RECALL
SOFTWARE DETECT COLUMN IO
A13
- A0
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
INPUT BUFFERS
DQ 1
COLUMN DEC RTC
A 0 A 1 A 2 A 3 A 4 A 10
x1 x2
INT
MUX
A14
- A0
OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-06431 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 29, 2007
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PRELIMINARY
Pin Configurations
V CAP NC A 14 A 12 A7 A6 A5 INT A4 NC NC NC V SS V RTCbat DQ0 A3 A2 A1 A0 DQ1 DQ2 X1 X2 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41
CY14B256K
V CC NC HSB WE A 13 A8 A9 NC A 11 NC NC NC V SS NC V RTCcap DQ 6 OE A 10 CE DQ7 DQ5 DQ4 DQ3 V CC
48-SSOP
Top View
(Not To Scale)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Pin Definitions
Pin Name A0-A14 NC WE CE OE X1 X2 VRTCcap VRTCbat INT VSS VCC HSB VCAP IO Type Input Description Address Inputs used to select one of the 32,768 bytes of the nvSRAM.
DQ0-DQ7 Input/Output Bidirectional Data IO lines. Used as input or output lines depending on operation. No Connect No Connects. This pin is not connected to the die. Input Input Input Output Input Write Enable Input, active LOW. When selected LOW, enables data on the IO pins to be written to the address location latched by the falling edge of CE. Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE high causes the IO pins to tri-state. Crystal Connection, drives crystal on start-up. Crystal Connection for 32.768-kHz crystal.
Power Supply Capacitor-supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used) Power Supply Battery-supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used) Output Ground Interrupt Output. Can be programmed to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH (push/pull) or LOW (open-drain). Ground for the device. Must be connected to ground of the system.
Power Supply Power Supply inputs to the device. Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected. (Connection Optional) Power Supply AutoStoreTM Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.
Document Number: 001-06431 Rev. *E
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Device Operation
The CY14B256K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The CY14B256K supports infinite reads and writes just like a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200,000 STORE operations.
CY14B256K
the chip. A pull up must be placed on WE to hold it inactive during power up. Figure 1. AutoStoreTM Mode
V CC V CAP
V CAP
V CC
10k Ohm
WE
SRAM Read
The CY14B256K performs a READ cycle whenever CE and OE are low while WE and HSB are high. The address specified on pins A0-14 determines which of the 32,752 data bytes shall be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAA (READ cycle #1). If the READ is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and will remain valid until another address change or until CE or OE is brought high, or WE or HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common IO pins DQ0-7 be written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. OE must be kept high during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left low, internal circuitry will turn off the output buffers tHZWE after WE goes low.
To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B256K provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the CY14B256K will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY14B256K will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the CY14B256K will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY14B256K will remain disabled until the HSB pin returns high. If HSB is not used, it must be left unconnected. Page 3 of 23
AutoStore Operation
The CY14B256K stores data to nvSRAM using one of three storage operations. The three storage operations are Hardware Store - activated by HSB, Software Store - activated by an address sequence, and AutoStore - on device power down. AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B256K. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 1 shows the proper connection of the storage capacitor. VCAP for automatic store operation. Refer to the DC Electrical Characteristics on page 13 for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to Document Number: 001-06431 Rev. *E
0.1UF
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PRELIMINARY
Hardware RECALL (Power Up)
During power up, or after any low power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will be automatically initiated and will take tHRECALL to complete.
CY14B256K
and not WRITE cycles be used in the sequence. It is not necessary that OE be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations must be performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations.The RECALL operation in no way alters the data in the nonvolatile elements.
Software STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B256K software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence may be clocked with CE controlled READs or OE controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles Table 1. Mode Selection CE H L L L WE X H L H OE X L X L A13-A0 X X X 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63
Data Protection
The CY14B256K protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B256K is in a WRITE mode (both CE and WE low) at power up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power Standby Active Active Active ICC2
[1, 2, 3]
L
H
L
Active
[1, 2, 3]
Notes: 1. The six consecutive address locations must be in the order listed.WE must be HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 15 address lines on the CY14B256K, only the lower 14 lines are used to control software modes. 3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06431 Rev. *E
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Noise Considerations
The CY14B256K is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise. Clock Operations
CY14B256K
Low Average Active Power
CMOS technology provides CY14B256K which allows drawing less current when it is cycled at times longer than 50 ns. Figure 2 shows the relationship between ICC and READ and/or WRITE cycle time. Worst case current consumption is shown for commercial temperature range, VCC = 3.45V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B256K depends on the following items: 1. 1The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. The operating temperature. 5. The VCC level. 6. IO loading. Figure 2. Current vs. Cycle Time
The clock registers maintain time up to 9,999 years in one second increments. The user can set the time to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions that are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as 0 are currently not used and are reserved for future use by Cypress. Reading the Clock While the double buffered RTC register structure reduces the chance of reading incorrect data from the clock, you to halt internal updates to the CY14B256K clock registers before reading clock data to prevent the reading of data in transition. Stopping the internal register updates does not affect clock accuracy. The update process is stopped by writing a 1 to the read bit R (in the flags register at 0x7FF0), and will not restart until a 0 is written to the read bit. The RTC registers can then be read while the internal clock continues to run. Within 20 ms after a 0 is written to the read bit, all CY14B256K registers are simultaneously updated. Setting the Clock Setting the write bit W (in the flags register at 0x7FF0) to a 1 stops updates to the CY14B256K registers. The correct day, date, and time can then be written into the registers in 24 hour BCD format. The time written is referred to as the Base Time. This value is stored in nonvolatile registers and used in calculation of the current time. Resetting the write bit to 0 transfers those values to the actual clock counters, after which the clock resumes normal operation. Backup Power The RTC in the CY14B256K is used for permanently powered operation. Either the VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When primary power, VCC, fails and drops below VSWITCH the device will switch to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of clock operation with the primary source removed, the data stored in nvSRAM is secure, having been stored in the nonvolatile elements as power was lost. During backup operation the CY14B256K consumes a maximum of 300 nA at 2V. Capacitor or battery values must be chosen according to the application. Backup time values based on maximum current specs are shown in Table 2, RTC Backup Time. Nominal times are approximately 3 times longer. Table 2. RTC Backup Time Capacitor Value 0.1F 0.47F 1.0F Backup Time 72 hours 14 days 30 days
Real-Time-Clock Operation
nvTIME Operation The CY14B256K consists of internal registers that contain clock, alarm, watchdog, interrupt, and control functions. Internal double buffering of the clock and the clock/timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. Clock and Alarm Registers store data in BCD format.
Using a capacitor has the advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14B256K will
Document Number: 001-06431 Rev. *E
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only source current from the battery when the primary power is removed. The battery will not, however, be recharged at any time by the CY14B256K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. Stopping and Starting the Oscillator The OSCEN bit in calibration register at 0x7FF8 controls the starting and stopping of the oscillator. This bit is nonvolatile and shipped to customers in the enabled (set to 0) state. To preserve battery life while system is in storage OSCEN must be set to a 1. This will turn off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it will take approximately take 5 seconds (10 seconds max) for the oscillator to start. The CY14B256K has the ability to detect oscillator failure. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at address 0x7FF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for enabled status. If the OSCEN bit is enabled and the oscillator is not active, the OSCF bit is set. The user must check for this condition and then write a 0 to clear the flag. It must be noted that in addition to setting the OSCF flag bit, the time registers are reset to the Base Time (see the section Setting the Clock on page 5), which is the value last written to the timekeeping registers. The Control/Calibration register and the OSCEN bit are not affected by the oscillator failed condition. If the voltage on the backup supply (either VRTCcap or VRTCbat) falls below its minimum level, the oscillator may fail, leading to the oscillator failed condition, which can be detected when system power is restored. The value of OSCF must be reset to 0 when the time registers are written for the first time. This will initialize the state of this bit, which may have been set when the system was first powered on. Calibrating the Clock The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 kHz. Clock accuracy will depend on the quality of the crystal, usually specified to 35 ppm limits at 25C. This error could equate to +1.53 minutes per month. The CY14B256K employs a calibration circuit that can improve the accuracy to +1/-2 ppm at 25C. The calibration circuit adds or subtracts counts from the oscillator divider circuit. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x7FF8. Adding counts speeds the clock up; subtracting counts slows the clock down. The calibration bits occupy the five lower order bits in the control register 8. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit, where a 1 indicates positive calibration and a 0 indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary 1 is loaded into the register, only the first 2 minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore each
CY14B256K
calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is 4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. In order to determine how to set the calibration one may set the CAL bit in the flags register at 0x7FF0 to 1, which causes the INT pin to toggle at a nominal 512 Hz. Any deviation measured from the 512 Hz will indicate the degree and direction of the required correction. For example, a reading of 512.010124 Hz would indicate a +20 ppm error, requiring a -10 (001010) to be loaded into the Calibration register. Note that setting or changing the calibration register does not affect the frequency test output frequency. Alarm The alarm function compares user programmed values to the corresponding time-of-day values. When a match occurs, the alarm event occurs. The alarm drives an internal flag, AF, and may drive the INT pin if desired. There are four alarm match fields. They are date, hours, minutes, and seconds. Each of these fields also has a Match bit that is used to determine if the field is used in the alarm match logic. Setting the Match bit to 0 indicates that the corresponding field will be used in the match process. Depending on the Match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. The MSB of each alarm register is a Match bit. Selecting none of the Match bits (all 1s) indicates that no match is required. The alarm occurs every second. Setting the match select bit for seconds to 0 causes the logic to match the seconds alarm value to the current time of day. Since a match will occur for only one value per minute, the alarm occurs once per minute. Likewise, setting the seconds and minutes Match bits causes an exact match of these values. Thus, an alarm will occur once per hour. Setting seconds, minutes and hours causes a match once per day. Lastly, selecting all match values causes an exact time and date match. Selecting other bit combinations will not produce meaningful results; however the alarm circuit must follow the functions described. There are two ways a user can detect an alarm event, by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x7FF0 will indicate that a date and time match has occurred. The AF bit will be set to 1 when a match occurs. Reading the Flags/Control register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event. Watchdog Timer The watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the Watchdog Timer register. The counter consists of a loadable register and a free running counter. On power up, the watchdog time out value in register 0x7FF7 is loaded into the counter load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to 1. The counter is compared to the terminal value of 0. If the counter reaches this value, it causes an internal flag and an optional interrupt
Document Number: 001-06431 Rev. *E
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output. You can prevent the time out interrupt by setting WDS bit to 1 prior to the counter reaching 0. This causes the counter to be reloaded with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and flag never occurs. New time out values can be written by setting the watchdog write bit to 0. When the WDW is 0 (from the previous operation), new writes to the watchdog time out value bits D5-D0 allow the time out value to be modified. When WDW is a 1, writes to bits D5-D0 will be ignored. The WDW function allows a user to set the WDS bit without concern that the watchdog timer value will be modified. A logical diagram of the watchdog timer is shown in Figure 3. Note that setting the watchdog time out value to 0 would be otherwise meaningless and therefore disables the watchdog function. The output of the watchdog timer is a flag bit WDF that is set if the watchdog is allowed to time out. The flag is set upon a watchdog time out and cleared when the Flags/Control register is read by the user. The user can also enable an optional interrupt source to drive the INT pin if the watchdog time out occurs. Figure 3. Watchdog Timer Block Diagram
CY14B256K
to the device and tHRECALL delay (see AutoStore/Power Up RECALL on page 16). Interrupts The CY14B256K provides three potential interrupt sources. They include the watchdog timer, the power monitor, and the clock/calendar alarm. Each can be individually enabled and assigned to drive the INT pin. In addition, each has an associated flag bit that the host processor can use to determine the cause of the interrupt. Some of the sources have additional control bits that determine functional behavior. In addition, the pin driver has three bits that specify its behavior when an interrupt occurs. The three interrupts each have a source and an enable. Both the source and the enable must be active (true high) in order to generate an interrupt output. Only one source is necessary to drive the pin. The user can identify the source by reading the Flags/Control register, which contains the flags associated with each source. All flags are cleared to 0 when the register is read. The flags will be cleared only after a complete read cycle (WE high); The power monitor has two programmable settings that are explained in the power monitor section. Once an interrupt source is active, the pin driver determines the behavior of the output. It has two programmable settings as shown in the following sections. Pin driver control bits are located in the interrupts register. According to the programming selections, the pin can be driven in the backup mode for an alarm interrupt. In addition, the pin can be an active LOW (open-drain) or an active HIGH (push-pull) driver. If programmed for operation during backup mode, it can only be active LOW. Lastly, the pin can provide a one shot function so that the active condition is a pulse or a level condition. In one shot mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In level mode, the pin goes to its active polarity until the Flags/Control register is read by the user. This mode is intended to be used as an interrupt to a host microcontroller. The Interrupt register is initialized to 00h. The control bits are summarized as follows: Watchdog Interrupt Enable - WIE. When set to 1, the watchdog timer drives the INT pin as well as an internal flag when a watchdog time out occurs. When WIE is set to 0, the watchdog timer affects only the internal flag. Alarm Interrupt Enable - AIE. When set to 1, the alarm match drives the INT pin as well as an internal flag. When set to 0, the alarm match only affects to internal flag. Power Fail Interrupt Enable - PFE. When set to 1, the power fail monitor drives the pin as well as an internal flag. When set to 0, the power fail monitor affects only the internal flag. High/Low - H/L. When set to a 1, the INT pin is active HIGH and the driver mode is push pull. The INT pin can drive high only when VCC > VSWITCH. When set to a 0, the INT pin is active LOW and the drive mode is opendrain. Active LOW (open drain) is operational even in battery backup mode. Pulse/Level - P/L. When set to a 1 and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a 0, the INT pin is driven high or low (determined by H/L) until the Flags/Control register is read. When an enabled interrupt source activates the INT pin, an external host can read the Flags/Control register to determine Page 7 of 23
Oscillator
32,768 KHz
Clock Divider
32 Hz
1 Hz
Counter
Zero Compare
WDF
WDS
Load Register
D Q
WDW
Q
write to Watchdog Register
Watchdog Register
Power Monitor The CY14B256K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to various thresholds. As described in the AutoStore Operation on page 3, when VSWITCH is reached as VCC decays from power loss, a data store operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. When operating from the backup source, no data may be read or written and the clock functions are not available to the user. The clock continues to operate in the background. Updated clock data is available to the user after VCC has been restored
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the cause. Remember that all flags will be cleared when the register is read. If the INT pin is programmed for Level mode, then the condition will clear and the INT pin will return to its inactive state. If the pin is programmed for Pulse mode, then reading the flag also will clear the flag and the pin. The pulse will not complete its specified duration if the Flags/Control register is read. If the INT pin is used as a host reset, then the Flags/Control register must not be read during a reset.
CY14B256K
During a power on reset with no battery, the interrupt register is automatically loaded with the value 24h. This causes power fail interrupt to be enabled with an active low pulse. Flags Register - The Flags register has three flag bits: WDF, AF, and PF. These flag bits are initialized to 00h. These flags are set by the watchdog time out, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. The flags are automatically reset once the register is read.
Figure 4. RTC Recommended Component Configuration
WDF Watchdog Timer WIE PF Power Monitor VINT H/L AF Clock Alarm AIE PFE P/L Pin Driver
VCC
INT
VSS
WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low
Recommended Values Y1 = 32.768KHz RF = 10M Ohm C1 = 0 C2 = 56 pF
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Table 3. RTC Register Map BCD Format Data Register 0x7FFF 0x7FFE 0x7FFD 0x7FFC 0x7FFB 0x7FFA 0x7FF9 0x7FF8 OSCEN 0x7FF7 0x7FF6 0x7FF5 0x7FF4 0x7FF3 0x7FF2 0x7FF1 0x7FF0 WDF WDS WIE M M M M 0 WDW AIE 0 0 PFE 0 H/L 10s Alarm Date 10s Alarm Hours 10 Alarm Minutes 10 Alarm Minutes 10s Centuries AF PF OSCF 0 0 0 0 0 0 D7 D6 0 0 0 0 D5 0 D4 10s Months 0 0 D3 D2 D1 Years Months Day Of Month Day of week Hours Minutes Seconds Calibration WDT P/L 0 0 Alarm Day Alarm Hours Alarm Minutes Alarm, Seconds Centuries CAL W R D0
CY14B256K
Function/Range Years: 00-99 Months: 01-12 Day of Month: 01-31 Day of week: 01-07 Hours: 00-23 Minutes: 00-59 Seconds: 00-59 Calibration Values [4] Watchdog [4] Interrupts [4] Alarm, Day of Month: 01-31 Alarm, Hours: 00-23 Alarm, Minutes: 00-59 Alarm, Seconds: 00-59 Centuries: 00-99 Flags [4]
10s Years
10s Day of Month 0 10s Minutes 10s Seconds Cal Sign 10s Hours
Table 4. Register Map Detail Time Keeping - Years D7 D6 D5 10s Years 0x7FFF D4 D3 D2 Years D1 D0
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Time Keeping - Months D7 0 D6 0 D5 0 D4 10s Month D3 D2 Months D1 D0
0x7FFE
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Time Keeping - Date D7 0 D6 0 D5 D4 D3 D2 D1 D0 10s Day of Month Day of Month
0x7FFD
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Leap years are automatically adjusted for. Time Keeping - Day D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 Day of Week D0
0x7FFC
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date.
Note: 4. Is a binary value, not a BCD value.
Document Number: 001-06431 Rev. *E
Page 9 of 23
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PRELIMINARY
Table 4. Register Map Detail (continued) Time Keeping - Hours D7 12/24 0x7FFB D6 0 D5 10s Hours D4 D3 D2 Hours
CY14B256K
D1
D0
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Time Keeping - Minutes D7 0 D6 D5 10s Minutes D4 D3 D2 Minutes D1 D0
0x7FFA
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Time Keeping - Seconds D7 0 D6 D5 10s Seconds D4 D3 D2 Seconds D1 D0
0x7FF9
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Calibration/Control D7 D6 0 D5 Calibration Sign D4 D3 D2 Calibration D1 D0 OSCEN
0X7FF8 OSCEN
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator saves battery/capacitor power during storage. On a no-battery power up, this bit is set to 0.
Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. Sign Calibration These five bits control the calibration of the clock. WatchDog Timer D7 0x7FF7 WDS WDS D6 WDW D5 D4 D3 WDT D2 D1 D0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0. Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5-WDT0) so it cannot be written. This allows the user to strobe the watchdog without disturbing the time-out value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be loaded on the next internal watchdog clock after the write cycle is complete. This function is explained in more detail in the watchdog timer section. Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32-Hz count (31.25 ms). The minimum range or time-out value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was cleared to 0 on a previous cycle.
WDW
WDT
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Table 4. Register Map Detail (continued) Interrupt Status/Control D7 0x7FF6 WIE AIE PFIE H/L P/L WIE D6 AIE D5 PFIE D4 0 D3 H/L D2 P/L
CY14B256K
D1 0
D0 0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin as well as the WDF flag. When set to 0, the watchdog time-out affects only the WDF flag. Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the alarm match only affects the AF flag. Power Fail Enable. When set to 1, the alarm match drives the INT pin as well as the PF flag. When set to 0, the power fail monitor affects only the PF flag. High/Low. When set to a 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW. Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register is read. Alarm - Day D7 M D6 0 D5 D4 D3 D2 D1 Alarm Date D0 10s Alarm Date
0x7FF5 M
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value. Alarm - Hours D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Hours Alarm Hours
0x7FF4 M
Contains the alarm value for the hours and the mask bit to select or deselect the hours value. Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Minutes Alarm Minutes
0x7FF3 M
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value. Alarm - Seconds D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Seconds Alarm Seconds
0x7FF2 M
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds' value. Match. Setting this bit to 0 causes the seconds' value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. Time Keeping - Centuries D7 D6 0 D5 D4 D3 D2 D1 Centuries D0
0x7FF1
0
10s Centuries
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Table 4. Register Map Detail (continued) Flags D7 0x7FF0 WDF AF PF OSCF WDF D6 AF D5 PF D4 OSCF D3 0 D2 CAL
CY14B256K
D1 W
D0 R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags/Control register is read. Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags/Control register is read. Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold VSWITCH. It is cleared to 0 when the Flags/Control register is read. Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation. This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip will not clear this flag. This bit survives power cycles. Calibration Mode. When set to 1, a 512-Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up. Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then write them with updated values. Setting the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters. The W-bit enables writes to RTC, Alarm, Calibration, Interrupt, and Flag registers. Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register. The user can then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.
CAL W
R
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. For user guidelines, not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND.......... -0.5V to 4.1V Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Input Voltage ............................................ -0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential...................-2.0V to VCC + 2.0V
CY14B256K
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [5] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.45V 2.7V to 3.45V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.45V) [6, 7, 8] Parameter ICC1 Description Test Conditions Commercial Min Max 65 55 50 Unit mA mA mA
Average VCC Current tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0mA. Average VCC Current All Inputs Don't Care, VCC = Max during STORE Average current for duration tSTORE Average VCC Current WE > (VCC - 0.2). All other inputs cycling. at tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate. Values obtained without output loads. 25C typical Average VCAP Current during AutoStore Cycle All Inputs Don't Care, VCC = Max Average current for duration tSTORE
Industrial
mA 55 (tRC = 45 ns) mA mA 3 10 mA mA
ICC2 ICC3
ICC4
3
mA
ISB
VCC Standby Current WE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0MHz. Input Leakage Current Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOUT = -2 mA Output LOW Voltage IOUT = 4 mA Storage Capacitor Between VCAP pin and VSS, 5V Rated 17 VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH -1 -1 2.0 VSS - 0.5 2.4
3
mA
IIX IOZ VIH VIL VOH VOL VCAP
+1 +1 VCC + 0.3 0.8
A A V V V
0.4 120
V F
Notes: 5. Outputs shorted for no more than one second. No more than one output shorted at a time. 6. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 3V. Not 100% tested. 7. The HSB pin has IOUT = -10 A for VOH of 2.4 V, this parameter is characterized but not tested. 8. The INT pin is open-drain and does not source or sink current when Interrupt Register bit D3 is low.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Capacitance [9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max 7 7
CY14B256K
Unit pF pF
Thermal Resistance [9]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA / JESD51. 48-SSOP TBD TBD Unit C/W C/W
JA JC
AC Test Loads
R1 577 3.0V OUTPUT 30 pF R2 789 3.0V OUTPUT 5 pF R2 789 R1 577
for tri-state specs
AC Test Conditions
Input Pulse Levels.................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%) ....................... <5 ns Input and Output Timing Reference Levels....................1.5 V
Note: 9. These parameters are guaranteed but not tested.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
AC Switching Characteristics
Parameter Cypress Alt. Parameter Parameter SRAM Read Cycle tACE tRC tAA
[10] [11]
CY14B256K
25ns part Description Min Max
35ns part Min Max
45ns part Min Max Unit
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR
[12] [12] [12]
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 0 3 3 25
25 35 25 12 3 3 10 0 10 0 25
35 45 35 15 3 3 13 0 13 0 35
45
ns ns
45 20
ns ns ns ns
tDOE tOHA [11] tLZCE tHZCE
15
ns ns
tLZOE [12] tHZOE [12] tPU tPD tWC tPWE tSCE tSD tHD tAW tSA tHA tLZWE
[9] [9]
15
ns ns
45
ns
SRAM Write Cycle Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Set-Up to End of Write Data Hold After End of Write Address Set-Up to End of Write Address Set-Up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write 3 25 20 20 10 0 20 0 0 10 3 35 25 25 12 0 25 0 0 13 3 45 30 30 15 0 30 0 0 15 ns ns ns ns ns ns ns ns ns ns
tHZWE [12, 13] tWZ tOW
Notes: 10. WE must be HIGH during SRAM Read Cycles. 11. Device is continuously selected with CE and OE both Low. 12. Measured 200 mV from steady state output voltage. 13. If WE is Low when CE goes Low, the outputs remain in the High Impedance State.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
AutoStore/Power Up RECALL
CY14B256K Parameter tHRECALL VSWITCH tVCCRISE
[14]
CY14B256K
Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time
Min
Max 20 12.5 2.65
Unit ms ms V s
tSTORE [15, 16]
150
Software Controlled STORE/RECALL Cycle [17, 18]
25ns part Parameter tRC tAS tCW tGHAX tRECALL tSS [19, 20] Description STORE/RECALL Initiation Cycle Time Address Set-Up Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time Min 25 0 20 1 100 70 Max 35ns part Min 35 0 25 1 100 70 Max 45ns part Min 45 0 30 1 100 70 Max Unit ns ns ns ns s s
Hardware STORE Cycle
CY14B256K Parameter tDELAY tHLHX
[21]
Description Time allowed to complete SRAM Cycle Hardware STORE Pulse Width
Min 1 15
Max 70
Unit s ns
RTC Characteristics
Parameter IBAK
[22]
Description RTC Backup Current
Test Conditions Commercial Industrial Commercial Industrial Commercial Industrial @Min. Temperature from Power up or Enable Commercial @25C Temperature from Power up or Enable Commercial @Min. Temperature from Power up or Enable Industrial @25C Temperature from Power up or Enable Industrial
Min
Max 300 350
Unit nA nA V V V V sec sec sec sec
VRTCbat [23] RTC Battery Pin Voltage VRTCcap tOCS
[24]
1.8 1.8 1.2 1.2
3.3 3.3 2.7 2.7 10 5 10 5
RTC Capacitor Pin Voltage RTC Oscillator Time to Start
Notes: 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE will take place. 16. Industrial Grade Devices require 15 ms Max 17. The software sequence is clocked with CE-controlled or OE-controlled READs. 18. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. 19. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 20. Commands like STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command. 21. Read and Write cycles in progress before HSB are given this amount of time to complete. 22. From either VRTCcap or VRTCbat. 23. Typical = 3.0V during normal operation. 24. Typical = 2.4V during normal operation.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled [10, 11, 25]
CY14B256K
tRC
ADDRESS
t AA t OH
DQ (DATA OUT) DATA VALID
Figure 6. SRAM Read Cycle #2: CE and OE Controlled [10, 25]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
DQ (DATA OUT)
tLZOE t PU
tDOE
DATA VALID
tHZOE
ACTIVE
ICC
STANDBY
Note: 25. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle #1: WE Controlled [25, 26]
CY14B256K
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 8. SRAM Write Cycle #2: CE Controlled
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Note: 26. CE or WE must be > VIH during address transitions.
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Switching Waveforms (continued)
Figure 9. AutoStore/Power Up RECALL
STORE occurs only if a SRAM write has happened
CY14B256K
VCC VSWITCH
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Figure 10. CE-controlled Software STORE/RECALL Cycle [18]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
ttGLAX GHAX
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Switching Waveforms (continued)
Figure 11. OE-controlled Software STORE/RECALL Cycle [18]
CY14B256K
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tSA
OE
tSCE
ttGHAX GLAX
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Figure 12. Soft Sequence Processing [19, 20]
Soft Sequence Command
ADDRESS
ADDRESS # 1 ADDRESS # 6
34 t SS
Soft Sequence Command
ADDRESS # 1 ADDRESS # 6
34 t SS
VCC
Figure 13. Hardware STORE Cycle
HSB (IN)
tHLHX tSTORE
HIGH IMPEDANCE
HSB (OUT)
tHLBL
HIGH IMPEDANCE
t DELAY
DQ (DATA OUT) DATA VALID DATA VALID
Document Number: 001-06431 Rev. *E
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PRELIMINARY
PART NUMBERING NOMENCLATURE CY 14 B 256 K - SP 25 X C T
Option: T - Tape & Reel Blank - Std.
CY14B256K
Pb-Free
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Data Bus: K - x8 + RTC Density: 256 - 256 Kb
Package: SP - 48 SSOP
Voltage: B - 3.0V
NVSRAM 14 - AutoStore + Software Store + Hardware Store
Cypress
Ordering Information
All of the above mentioned parts are of "Pb-free" type. Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts. Speed (ns) 25 35 45 45 Ordering Code CY14B256K-SP25XCT CY14B256K-SP35XCT CY14B256K-SP45XCT CY14B256K-SP45XIT CY14B256K-SP45XI Package Diagram 51-85061 51-85061 51-85061 51-85061 51-85061 48-pin SSOP 48-pin SSOP 48-pin SSOP 48-pin SSOP 48-pin SSOP Package Type Operating Range Commercial Commercial Commercial Industrial
Document Number: 001-06431 Rev. *E
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PRELIMINARY
Package Diagrams
Figure 14. 48-pin Shrunk Small Outline Package, 51-85061
CY14B256K
51-85061-*C
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
Document Number: 001-06431 Rev. *E
Page 22 of 23
(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY14B256K, 256-Kbit (32K x 8) nvSRAM with Real-Time-Clock Document Number: 001-06431 REV. ** *A *B ECN NO. 425138 437321 471966 Issue Date See ECN See ECN See ECN Orig. of Change TUP TUP TUP New Data Sheet Show Data Sheet on external Web Description of Change
CY14B256K
Changed VIH(MIN) from 2.2V to 2.0V Changed tRECALL from 60s to 100s Changed Endurance from 1Million Cycles to 500K Cycles Changed Data Retention from 100 Years to 20 Years Added Soft Sequence Processing Time Waveform Updated Part Numbering Nomenclature and Ordering Information Added RTC Characteristics Table Added RTC Recommended Component Configuration Changed from "Advance" to "Preliminary" Changed the term "Unlimited" to "Infinite" Changed endurance from 500K cycles to 200K cycles Device operation: Tolerance limit changed from +20% to +15% in the "Features Section" and "Operating Range Table" Removed Icc1 values from the DC table for 25 ns and 35 ns industrial grade Changed VSWITCH(MIN) from 2.55V to 2.45V Added temperature spec. to data retention - 20 years at 55C Updated "Part Nomenclature Table" and "Ordering Information Table" Removed VSWITCH(min) spec from the AutoStore/Power Up RECALL table Changed tGLAX spec from 20ns to 1ns Added tDELAY(max) spec of 70s in the Hardware STORE Cycle table Removed tHLBL specification Changed tSS specification form 70s(min) to 70s(max) Changed VCAP(max) from 57F to 120F Added footnote #7 related to HSB Added footnote #8 related to INT pin Changed tGLAX to tGHAX Removed ABE bit from Interrupt register
*C
503277
See ECN
PCI
*D
597004
See ECN
TUP
*E
696097
See ECN
VKN
Document Number: 001-06431 Rev. *E
Page 23 of 23
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